The present disclosure is related to semiconductor devices and their methods of manufacture; and, more particularly, to the devices and manufacture of metal oxide semiconductors and thyristors.
The advancement of the semiconductor industry has brought forward devices of smaller geometries and high density for enabling higher levels of integration. Some of these developments have typically required multiple processing steps and procedures, which can affect their production efficiencies and economics.
A common element in a semiconductor device is a transistor, such as a metal-oxide-semiconductor field-effect transistor (MOSFET). These MOSFETs can be interconnected to other elements on a substrate to form part of an overall electrical circuit such as a memory, a control unit, a network device, a processor or handheld electrical product etc. As the dimensions of these MOSFETs shrink, they can become more vulnerable to source to drain leakage in the semiconductor region under the gate oxide. This leakage can be due to punch through or sub threshold leakage. One method to reduce these leakage mechanisms is to use a Silicon On Insulator (SOI) substrate such as a layer of silicon on oxide where the silicon layer may be thin enough such that a bias of a gate electrode may be capable of fully depleting the silicon layer. Such devices may be described as fully depleted SOI.
One technique that can be used to guard against the breakdown or device degradation from hot carrier injection (HCI) of a gate oxide for a MOSFET is the formation of drain/source extension(s), known alternatively as lightly doped drain (LDD) regions. These regions can be formed in an upper surface region of the semiconductor material and/or with lighter doping than the source drain regions of the MOSFET and may extend laterally beneath the gate and between the channel and their respective source and drain regions. For example, such devices may comprise relative concentration differences as may be presented by S/D regions of concentrations in the Xe20 range, LDD regions with concentrations from about Xe18 to Xe19 and channel regions with concentration of about Xe17. During operation of such MOSFET, the resistance of the extension regions can provide voltage drops along their length that may be sufficient to enable the MOSFET to withstand higher voltage operation.
Another contribution to the evolution of smaller geometry devices has been the advent of silicon-on-insulator technology. MOSFETs formed on conventional Silicon-on-insulators (SOI) exhibit lower parasitic junction capacitance, greater on/off isolation and better sub-threshold swing in comparison to their equivalent bulk counterparts. With these performance advantages, the SOI devices can perform with lower power, higher speed and improved switching characteristics.
For SOI MOSFETs, it may be desirable to form a thin silicon layer for the channel regions so that the channel region may be fully depleted. At the same time, there may be an opposing desire, to enhance the thickness of their source and drain regions for lower resistance. The thicker the source drain regions the thicker the salicide layer formed on them can be. The thicker the salicide layer the lower the salicide resistance. To accommodate these dual objectives for a thin channel region and thicker source drain regions, raised structures may be formed over the source/drain regions. These raised source and drain structures may be formed through either the use of epitaxial deposition or trench formations for recessed gates. By elevating the source and drain regions, metal diffusion during silicide formation need not consume their full thickness. Typically the silicide, epitaxial deposition and implant processes might each be performed using separate patterning provisions. They may be patterned for placing silicide and/or epitaxial material offset from the source/drain extension regions. By such offset, manufacturing tolerances may be accommodated during their fabrication such that the silicide and/or epitaxial material might not overlap the extension regions. Accordingly, it may be noted that an overall length of a MOSFET could thus be limited by the manufacturing tolerances of the various mask patternings associated with the separate silicide, epi and/or implant masks.
In the case of fabricating thin capacitively coupled thyristor (TCCT) devices, there may be a need to silicide the anode/cathode-emitter regions. Additionally, an electrode over one of the base regions might need to be formed with an offset relative to its other base region. Such offset may allow operation of the electrode with reduced likelihood of gate induced leakage (GIDL) effects relative to the offset base region. Typically, fabrication of the offset base might require separate masking provisions to assure its offset relationship relative to the gate electrode. Additionally, silicide patterning might also use its own masking provisions for forming the silicide with clearance from the electrode and the base regions. For if the salicide were to overlap two thyristor regions, the shorting by the silicide could destroy thyristor operation.
It may be noted that these separate patterning and masked provisions for the source/drain extensions, silicide and/or epi structures for a MOSFET, may each add to the complexity, cost and size of the overall device. Likewise, it may be noted, that the separate mask provisions for definition of the offset base, the emitter silicide and/or the epi structures for the thin capacitively coupled thyristor may similarly add to its overall complexity, cost and size.